3
3
5
5
3
3
Days
1
1
8
8
Hours
2
2
5
5
Minutes
0
0
5
5
Seconds
Days left until PCB West 2018
FacebookFacebook
TwitterTwitter
LinkedInLinkedIn
CONFERENCE QUESTIONS CONTACT
Jennifer Schuler at jschuler@upmediagroup.com • 918-496-1476


 

Day-by-Day Conference Program

 

 

Tuesday Sept 12th

Tuesday, September 12th
8:30 a.m.
Conference Coffee Break, sponsored by Prototron Circuits
9:00 a.m. – 10:00 a.m.
1: Advancements in MCAD-ECAD Co-Design – Ensuring All ECAD Data are Exchanged Seamlessly to Reduce Iterations
Speaker: Vince Di Lello, Cadence

Consumer IoT and Industrial IoT are increasing the number of flex and rigid-flex designs in the industry. At the same time, complexity of designing flex and rigid-flex designs is increasing as improvements are made in the manufacturing process. Since many of the flex and rigid-flex designs have to fit into tight enclosures with imaginative and impressive ways to bend and fold the flex portion, it is important to ensure the details of flex and rigid-flex designs are passed accurately and efficiently between the ECAD and MCAD teams. What if your design tool made the communication between those two worlds more efficient? Using accurate and detailed STEP models, including enclosures from the MCAD team, mechanical intent, including transformation of the flex sections, can now be articulated and physical conflict issues resolved directly from within the ECAD tool. This presentation will demonstrate how your design tool can assist in overcoming issues, as well as save time and iterations by bringing system-level 3D MCAD views and checks directly to the PCB designer’s desktop

Who should attend: PCB Designers, System Designers, Hardware Engineers, Fabricator Engineers/Operators, Assembly Engineers/Operators, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner
 
2: Intelligent DfM
Speaker: Kevin Webb, Mentor Graphics

Design for Manufacturing (DfM) applications have been around for a while and have helped many companies reduce product costs, improve quality and get products to market faster. PCB technology and manufacturing processes have become more complex and varied, however, making it difficult to create a simple set of DfM rules. In this session we will discuss a new approach to implementing DfM analysis. DfM applications today must be able to make intelligent decisions for the user about what DfM checks are relevant for their PCB materials and technology, all while considering the manufacturing processes to be used in the production. Those applications achieving this objective will serve their users better and make the benefits of DfM attainable by a larger audience.

Who should attend: Assembly Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
9:00 a.m. – 11:00 a.m.
3: Power Distribution Made Easy
Speaker: Dan Beeker, Freescale Semiconductor

This presentation will present a simple EM physics and geometry-based approach to designing power distribution networks on PCBs. From input power connection to the IC die, the simple rules discussed can be used to reduce power supply noise and improve EMC.

This course covers the following topics: how the EMI/EMC tests are conducted and how to avoid many configuration layout problems; design techniques to minimize radiation/susceptibility for both digital and analog PCBs; grounding and shielding techniques; and how to overcome radiation problems with connectors, cables, and hardware slots.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
4: Layout of Switch Mode Power Supplies
Speakers: Rick Hartley, RHartley Enterprises

When executing PCB layout, we tend to treat digital circuits differently from analog circuits. Each has its own critical requirements. Switch mode power supplies are another wrinkle altogether and usually need to be treated differently from either analog or digital structures. All switch mode power supplies have four to five circuit loops, all of which are important, but a couple of these loops are downright critical in terms of PCB layout. An improperly designed switch mode supply often will not function as intended, and in some cases, not at all. In contrast, understanding what makes up a switcher circuit and knowing how to take care of the loops during PCB layout will allow these supplies to operate flawlessly, and with very high efficiency.

This course will outline the difference between switchers and series regulated supplies, the different types of switcher circuits (buck, boost, etc.), basic theory of operation of switcher circuits and the impact of the various components, definition and behavior of the five loops, layout to isolate loops from one another to minimize voltage drop and to control current paths, layout to minimize noise and EMI, effect of paralleling output capacitors and proper grounding technique.

Who should attend: PCB Designers, Circuit/Hardware Engineers, SI Engineers, System Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
9:00 a.m. – 12:00 noon
5: Flexible Circuits from Design through Test: Lessons Learned
Speaker: Mark Finstad, Flexible Circuit Technologies, and Nick Koop, TTM Technologies

This course will cover the entire gamut of flexible and rigid flex circuits from two of the most recognized names in the industry; Mark Finstad (co-chair of IPC-2223) and Nick Koop (co-chair of IPC-6013). Topics covered will include mechanical design/material selection, cost drivers, bending and forming concerns, testing, and issues unique to rigid flex. Throughout the presentation, the instructors will share many real life stories of flexible circuit applications gained over 30 years in the industry. Some of these are success stories and others not so much, but all provide excellent lessons learned. The instructors also welcome and encourage questions, and enjoy “wandering off course” with lively interactive discussions on specific topics from the class.

Who should attend: PCB Designers, Fabricator Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
9:00 a.m. – 5:00 p.m.
6: The Basics of PCB Design
Speaker: Susy Webb, Fairfield Industries

This presentation will go through the entire process of designing a board, including discussing good ways of designing library components for manufacturability and basic placement methods and scenarios, with some tips from seasoned designers. Additionally, we will discuss ideas for successful plane placement and division, plenty of routing ideas and conventions, and manufacturing guidelines for all. Finally, we will conclude with what is needed to finish the boards, send out all the files needed, and save the designs.

Who should attend: PCB Designers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
7: Key Issues for EMI/EMC: How to Design and Build a Compliant System
Speaker: Robert Hanson, Americon

If you are a design engineer, it pays to know how and why EMI testing is conducted, as well as the typical causes of failure. This course provides ways to prevent common EMI/EMC problems regarding power supplies, cables, connectors, slots, discontinuity of ground planes and more. The focus is on EMI and RFI issues regarding PCBs, as well as relevant EMI regulations in the US and the European Union. Highlights include PCB radiation basics, radiation, and bypass on PCBs, PCB radiation suppression techniques, grounding designs/filtering, crosstalk/termination, power and ground planes, antenna loops, spread spectrum clocking, and differential mode and common-mode radiation. This course covers the following topics: how the EMI/EMC tests are conducted and how to avoid many configuration layout problems; design techniques to minimize radiation/susceptibility for both digital and analog PCBs; grounding and shielding techniques; and how to overcome radiation problems with connectors, cables, and hardware slots.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
 
8: Troubleshooting and Defect Resolution of SMT Assembly Processes
Speaker: Jim Hall and Phil Zarrow, ITM Consulting

We don’t assemble electronics in a perfect world. Defects happen. This course examines failures and root cause analysis of PCBA defects, starting with a clear definition of the generic types of defects and their impact, such as non-function, reduced reliability, etc. Detection and determination methodologies and procedures will be discussed. Attributes of specific processes and equipment centers, as well as materials that can contribute to defect generation are identified. Specific defects are then analyzed using these background methodologies: e.g., type of defect and impacts, detection methods, possible contributing causes, etc. Finally, general strategies and guidelines for preventing defects will be presented. This seminar is for anyone involved in directing, developing, managing and/or executing failure and root cause analysis and defect resolution, including managers, engineers and others in manufacturing, quality and design.

Who should attend: Hardware Engineers, Assembly Engineers/Operators, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
10:00 a.m. – 11:00 a.m.
9: Leveraging Data Management for a Competitive Advantage
Speaker: Craig Armenti, Mentor Graphics

You probably don’t often think of data management when you think about creating and sustaining a competitive advantage. Yet data management is a critical element of efficient library development, modular circuit design and formal design reuse (just to name a few), all of which have been proven to- improve time to market, reduce product development cost, and improve design quality. Efficient data management is key to achieving a competitive advantage, especially with large, sometimes globally distributed teams. Proper data management techniques and workflows can ensure the quality, integrity and security of the data used throughout the product development process. During this session we will discuss how to leverage library and design data management to create and sustain a competitive advantage. We will examine how data management can be used from initial system definition through the design process, to release to manufacturing. We will also discuss how integration between engineering and PLM and ERP systems can provide full lifecycle management of your libraries and designs.

Who should attend: PCB Designers, System Designers, Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner
 
10: Build Hardware Faster: 5 Rapid Prototyping Lessons Enterprises Can Learn from Startups
Speaker: Jeff McAlvay, Tempo Automation

The recent explosive growth in the number of hardware startups has fueled a movement to make hardware development as fast as software development. Hardware design and new product introduction (NPI) is now easier thanks to the availability of new software tools and automated low-volume manufacturing services. With an accelerated ability to build prototypes, hardware startups embracing the “building hardware faster” movement in turn are able to speed up their product iterations. This production trend has transformed many hardware startups into something more akin to a Lean software business, providing a competitive edge over larger hardware companies in terms of getting products to market faster. This session presents five lessons that will help enterprise businesses adopt rapid prototyping in their NPI projects, allowing them to innovate at the speed of a startup. We will explore how startups use the latest software tools and services to bring manufacturing intelligence into the design process and agile methods to integrate electronics, and mechanical and software development. Tempo Automation is the world’s first software-enabled robotic factory for PCB assembly, and is the rapid prototyping partner for many cutting-edge innovators in robotics, aerospace, electric and autonomous vehicles and IoT.

Who should attend: PCB Designers, Hardware Engineers, Assembly Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
 
12: Proactive Testability in the PCB Design Flow
Speaker: Mark Laing, Mentor Graphics

Traditionally, design for test (DfT) has been very reactive when PCB designs are created. Test engineers may get advanced notification of PDF schematics for review, but their feedback typically is considered late in the design cycle, during the routing phase of the design after many layout decisions have already been made. The consequences of this flow are that final PCB layouts are not optimized for test purposes; therefore, significant reliance is put on functional test to detect manufacturing defects. This then affects meeting delivery times, work in progress and, hence, manufacturing and test costs. This presentation will review these existing practices and discuss changes that can be undertaken to make testability decisions proactive, not reactive, in the design flow.

Who should attend: Assembly Engineers, Operators
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
12:00 noon – 1:00 p.m.
Streamline Circuits Lunch-n-Learn
(Tuesday Conference attendees and speakers only)
1:00 p.m. – 2:00 p.m.
13: Flex and Rigid-Flex PCBs
Speaker: Behrooz Shamsodini, NCAB Group USA

This seminar will provide an introduction to rigid-flex and flex PCBs. The topics covered will include an introduction to the features and benefits of flex and rigid-flex products defining the advantages and when these technologies should be considered for use. The development history will be briefly reviewed in the context of the material sets commonly used for various applications. The manufacturing process will be reviewed for rigid-flex boards to provide a better understanding of the limitations associated with mixed material sets. Design rules and product reliability will be introduced, as well as a review of basic capabilities for the prototype and volume production.

Who should attend: PCB Designers, System Designers, Fabricator Engineers/Operators, Assembly Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Intermediate
1:00 p.m. – 3:00 p.m.
14: Power Integrity and Decoupling Primer for PCB Designers
Speaker: Ralf Bruening, Zuken

Today, supply voltages decrease with every new silicon generation, contributing to the goal of reducing power consumption of electronics. This and the resulting shrinking noise margins for these ICs define increasing demands for the quality and stability of power distribution systems of PCBs. Hence, tighter requirements and constraints from silicon vendors are defined for the power distribution networks (PDN) PCB designers have to follow – in conjunction with tighter decoupling schemes. Board real estate limitations, application-dependent restrictions (e.g. discrete package allowance in automotive) and cost demands further complicate the game. In this two-hour workshop, the requirements and basics of PCB power distribution systems are explained in detail. Issues like plate capacitance, loop inductances and cavity resonance are explained without deep math. Side effects to the signal integrity and EMC behavior of board structures are discussed using illustrated practical examples. The role of decoupling capacitors and their evolution in recent years is a major part of the workshop. Guidelines for a first order covering and resolving power integrity issues are given, regardless of the PCB design and ECAD process used. Simulation capabilities addressing power-integrity during PCB design will be explained and demonstrated by slides in a generic vendor-neutral manner as a problem=solving approach. Silicon vendor support documents (e.g., constraint and spreadsheet tools) to address power integrity are introduced and discussed. Examples from various industries (e.g., automotive) will complement the session with practical application experience.

Who should attend: PCB Designers, Hardware Engineers, SI Engineers, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
1:00 p.m. – 4:30 p.m.
15: Effective PCB Design: Techniques to Improve Performance
Speaker: Dan Beeker, Freescale Semiconductor

As IC geometries continue to shrink and switching speeds increase, designing electromagnetic systems and printed circuit boards to meet the required signal integrity and EMC specifications has become even more challenging. A new design methodology is required. Specifically, the utilization of an electromagnetic physics-based design methodology to control the field energy in your design will be discussed. This training module will walk through the development process and provide you with guidelines for building successful, cost-effective printed circuit boards.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
16: Circuit Grounding to Control Noise and EMI
Speaker: Rick Hartley

When a time-varying (AC) current flows, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years, ICs with very fast rise-time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding can contain and control stray fields, making noise and EMI issues virtually nonexistent.

This course will cover clock vs. square wave frequency, the concept of “ground,” location of fields in the PCB, where high- and low-frequency currents flow, keys to controlling common mode EMI, cables and other radiators, source control of EMI, effects of IC style and packaging, impact of connector pin-out, effect of component positions, divided planes and plane islands in the PCB, routing to control noise, routing and the IO structure, board stackup, filtering and blocking for single-ended and differential lines, and three approaches to system RF shielding and grounding.

Who should attend: PCB Designers, Circuit/Hardware Engineers, SI Engineers, System Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
 
17: PCB Stackup Design and Material Selection
Speaker: Bill Hargin, Nanya

The objective of this course is to guide design teams – from hardware engineers to layout designers and fabricators – through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, reduced copper conductivity, surface roughness, as well as glass-weave skew.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers, Fabricator Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
2:00 p.m. – 3:00 p.m.
18: Improve Flexible Printed Circuit Manufacturing Productivity with Better DfM Checks
Speaker: Steve Watt, Zuken

Flexible printed circuits (FPC) are not new. Yet, FPC is a growing segment and presents some new design and manufacturing challenges. For example, FPCs require new and different manufacturing checks compared to a traditional rigid PCB. These new DfM checks can improve design quality and manufacturing yields. This session will cover the FPC design process and the manufacturing checks that can improve your design and its manufacturability.

Who should attend: PCB Designers
Course rating (Beginner, Intermediate, Advanced): Intermediate
3:00 p.m. – 4:00 p.m.
19: Rigid-Flex PCB Design – Practical Tips and Best Practices
Speaker: Craig Armenti, Mentor Graphics

Prior to the advent of rigid-flex PCBs, when a multi-board product included a flex PCB (or multiple flex PCBs), the flex was usually assigned to a flex design specialist. The flex PCB was designed separately from the rigid PCBs, with physical connectors used to assemble the rigid and flex boards into a product-level design. The flex designer was familiar with stackup and material options, along with the best practices for stiffeners and bends. There is, after all, a certain science to flex design that, when properly applied, can help ensure first-pass success. But how can a traditional rigid PCB designer who is not familiar with flex terminology, processes, and requirements ensure a high probability for first-pass success when assigned to a rigid-flex design? As with any new skill, education on terminology and best practices, along with access to tools that facilitate and ensure process compliance, is key. During this session we will discuss some of the fundamental best practices and guidelines a rigid-flex designer will need to become familiar with and adhere to in order to be successful.

Who should attend: PCB Designers
Course rating (Beginner, Intermediate, Advanced): Beginner
3:00 p.m. – 5:00 p.m.
20: How to Fight Magnetic Noise Gremlins
Speaker: Keven Coates, Geospace Technologies

Have you ever had a noise-sensitive circuit and tried to find the noise source? Even after you completely encased sensitive portions in all sorts of shielding, you still had noise? It’s very possible this is magnetic noise. Lower frequency magnetic fields cannot be contained and shielded against in the same way electric fields can. In this presentation, hear about the speaker’s nine-month-long battle with a specific magnetic noise issue, the best tools to fight it, twisted pair, current loops, and the best ways to test for and defeat magnetic noise in a design.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced

 

Wednesday Sept 13th

Wednesday, September 13th
8:30 a.m.
Conference Coffee Break, sponsored by Prototron Circuits
8:30 a.m. – 12:00 noon
21: The Complexities of Fine Pitch BGA Design
Speaker: Susy Webb, Fairfield Industries

Designing with BGAs is much more challenging than in the past. Ball pitches are going down, and total pin counts and package sizes are going up, making everything more complex. With those changes, signal integrity and EMI issues become more profound; fanout and routing are much more challenging, and power connections more difficult. Add to that the manufacturing concerns that have surfaced from small pad openings and tiny capacitors, and the designer has to face some complex issues. In this presentation, we will discuss all of those things and more, including choosing effective BGAs, placement for components and caps, grid systems for parts and routing, through-hole and microvia fanout possibilities, and manufacturing issues unique to these kinds of designs. This new and reworked class includes many illustrations and examples.

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Intermediate
9:00 a.m. – 11:00 a.m.
22: Multi-Board PCB Design - a Different Boundary Value Problem
Speaker: Ben Jordan, Altium

Aesthetics, ergonomics and industrial form are paramount design objectives, as new products must appeal to attention-starved consumer audiences. Intelligent people increasingly crave intelligent products. The desire to maximize production efficiency by consolidating all the electronics onto one board is at odds against higher mechanical design priorities. Add to that the desire markets inherently develop for configurations and optional extras, and it’s hard to avoid a multi-board design approach.


This technical session presents practical approaches to multi-board system-level PCB design, including partition boundaries, subcircuit relocation, interconnect methods, panels and layer stacks, rigid-flex and mechanical integration with enclosure design. Also covered: potential disaster areas and ways to avoid pitfalls, how to effectively manage connectivity, and improving manufacturing outputs for unambiguous fabrication and assembly.

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Beginner
9:00 a.m. – 11:00 a.m.
23: Signal Attenuation in Very High-speed Circuits
Speaker: Rick Hartley

In all high-speed/high-frequency circuits, signal integrity is dependent on a number of variables, all of which accumulate to impact the noise budget of the circuit. With very high-speed circuits, an even larger number of issues come into play, and all the effects are more extreme. Some problems are driven by design deficiencies, some by the physical structure and design of the ICs, and still more are driven by the PCB's copper style and base material parameters.

This course will outline all the effects impacting signal integrity at very high-speeds and will detail such items as via stubs, jitter, inter-symbol interference, impact of copper style on skin effect, loss tangent, impact of layer change during routing and other major signal integrity concerns, as well as the impact some of these items have on timing and the Y-axis attenuation of signal eyes. Also discussed will be solutions to these issues, including some new high-speed base materials.

Who should attend: Circuit/Hardware Engineers, SI Engineers, PCB Designers, System Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate, Advanced
 
24: Thermal Design Considerations for SMD PCBs
Speaker: Keven Coates, Geospace Technologies

By now everyone has seen those nice aluminum core PCBs that dissipate heat fantastically, but what do you do when all you have to work with is FR-4 and SMD components? How do you keep those MOSFETs and faster processors cool? How are semiconductor packages designed to rid heat? What’s the best way to utilize that? This class will go over basics such as thermal resistance, how airflow affects things, good design goals, estimating junction temperature, and how to pick the right components to minimize the temperature of the design and therefore maximize reliability.

Who should attend: PCB Designers, System Designers, Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced

9:00 a.m. – 12:00 noon
25: PCB Layout - Place and Route
Speaker: Mike Creeden, San Diego PCB

IWith today’s fast paced technology curve, everyone is learning various “islands of automation” for such topics as: DFX, material selection, high-speed-design, HDI (High-Density-Interconnect), software tool new features, signal/power analysis and many others. This class will show integration of “islands of automation” into the overall flow of design loosely referred to as place and route. Highlighting the most important aspect of the equation and that is the designer and improving design skills. Attendees will learn how and when the latest trends and technologies can be incorporated into the average CAD Layout process. They will observe solutions and real-life examples to complex challenges, learning how to improve the order of the layout process for maximum benefit. Topics covered include DfX with manufacturing collaboration to the CAD process flow; project build profile (type of circuit, end customer, environment, quantity, etc.); mechanical and 3D; constraints, SI/PI, HDI and stackup; placement methods (if placement is poor, routing is difficult or unsolvable); routing and power management methods; verification using “correct-by-construction” methods; documentation and deliverables.

Who should attend: PCB Designers, System Designers, Circuit/Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
10:00 a.m. – 11:00 a.m.
26: PCB as a Universal Microwave Component
Speaker: Milan Hammer, Mil1. Ltd.

Use of discrete passive components like inductors and capacitors in microwave and RF designs is strongly limited by their parasitics and their self-resonant frequency. That is one of the reasons why such components are often realized in the form of transmission lines on printed circuit boards. A simple, straightforward method to effectively replace discrete passive components by their transmission line equivalent is described in the first part of the presentation. All the transmission line equivalents shown in the presentation are realized in the form of microstrip lines. The main differences between the behavior of discrete passive components and their transmission line counterparts are explained with practical examples by comparing simulation results. No complex formulas are used in the presentation, so only basic knowledge of microwave techniques is required to understand the described method. The second part of the presentation is dedicated to transmission line structures that either do not have any discrete equivalent or their discrete equivalents have many limitations that cannot be used in practical designs. The presentation is an introduction into special microwave components realized purely by an appropriate PCB structure. It is recommended for designers who are not especially focused on RF/microwave design.

Who should attend: PCB Designers, Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate

10:00 a.m. – 2:00 p.m.
Booth Barista, sponsored by Zuken
11:00 a.m. – 12:00 noon
27: PCB Waterproofing: Why and How. Introducing a New Category of Technology to Solve the Problem.
Speaker: Edward Hughes, Aculon

The IPX standard provides a clearer picture of how water resistant a component is compared to vague marketing terms such as “waterproof.” In today’s competitive marketplace, where users are so attached to their electronic devices, water resistance isn’t sufficient anymore. Market intelligence firm IDC says liquid is the second most common cause of damage to smartphones. Increasingly, designers want to build water protection into the design to ensure product performance and reduce device failures. As a result of claims by several leading mobile brands, consumers now are looking for water resistance and protection as a feature of new and improved devices. Yet, it is known that unsealed PCBs absorb moisture from the air and can fail. Traditional approaches to protecting critical electronic components have been either insufficient or expensive. Consumers have had to rely on specialty cases to protect their devices, which took away from the integrity and functionality of the design. In the past few years, engineers have tried to seal devices with gaskets, but because most devices have several ports, it was a challenge to seal the device in an aesthetic manner. Even when successful, gaskets are prone to failure over time. Rather than addressing the issue from the inside out, surface modification technologies can be used as an outer skin of the PCB. These water-resistance technologies have generally fallen into two categories: conformal coatings that repel fluids but require some level of masking or "keep-out" areas, and vacuum-deposited coatings, which also require masking, such as parylene-based treatments. Both processes are tedious, complex and can be expensive. New novel surface treatments create a third category. It’s a no-mask solution based on proprietary hydro/oleophobic coatings that are implemented on an inline basis, and can provide the benefits of no masking and eliminate the need for costly capital investment and mitigate the bottlenecking batch process of vacuum-based manufacturing or masking operations.

Who should attend: PCB Designers, Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate / Advanced

 
28: Coplanar Waveguide Basics for Microwave PCB Design
Speaker: Eric Escalante, Analog Devices

As frequency requirement gets higher in designing an RF PCB, a different approach and tools could be used to meet the demand. A given solution is not always applicable to the next design to be worked on. This presentation aims to provide basic CPW design information geared toward a practicing microwave circuit designer, including the applicability and benefits of CPW transmission line configuration, and design and simulation modeling tips. Additionally, we will discuss the use of tools currently available, such as RFCOMP for schematic and layout, and simulation tools for signal integrity and performance verification.

Who should attend: PCB Designers, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner

 
29: Achieving Signal Integrity and Meeting EMI Radiation Requirements Using High-Speed Connectors
Speaker: Robert Hanson, Americon

Examples will be shown of connectors that have poor control of EMI radiation/immunity and also are affected by mutual inductance and high-signal reflection. Next, examples of ground pins will be shown that in turn enhance capacity. The ground blade connector will be shown with different signal/ground pin configurations to show comparative transmission capabilities. Two widely used high-speed connectors for circuit cards and backplanes will be compared. Then a method to interface a connector to a land trace to eliminate reflections will follow. Finally, a connector that passed radiated emissions up to 500MHz will be discussed.

Who should attend: Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate

 
30: Optimizing Reliability by Reducing Failures Due to Vibration and Acceleration
Speaker: David Wiens, Mentor Graphics

Fatigue-related design flaws can drive field failure rates as high as 20% in the first year, resulting in high levels of warranty claims and field returns. Reliability is particularly challenging for products that operate under extreme environmental stress, as well as those for whom maintenance is too costly or impossible. The traditional method of detecting fatigue due to stresses is “shake and bake” chambers used to perform highly accelerated lifecycle tests on a physical prototype. This approach is time-consuming, costly, physically destructive, and still only provides partial design coverage. This session will focus on improving a design flow to optimize reliability by finding vibration issues much earlier in the design process.

Who should attend: PCB Designers
Course rating (Beginner, Intermediate, Advanced): Beginner

12:00 p.m. – 1:00 p.m.
Lunch on the exhibit floor, sponsored by Sierra Circuits
1:00 p.m. – 2:00 p.m.
31: Practical Design Considerations for Particle Impact Dampers (PID) to Prevent Random Vibration Failures in Printed Circuit Boards
Speaker: Ron Hunt, Topline Components

Installation of a particle damper (PID) can often prevent fatigue failures in PCBs due to harsh vibration environments. PID is a simple, compact, and cheap solution with several inherent advantages over traditional mitigation methods used in the past. This presentation is intended to make the PCB design community aware of best practices and design principles to prevent severe vibration in PCBs, including guidance for sizing, placing, and mounting a particle damper. In simple terms, it also explains the physics involved and how to determine if a PID is likely to be an effective design solution to a particular vibration problem.

Who should attend: PCB Designers, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate

1:00 p.m. – 3:00 p.m.
32: An Intuitive Approach to Understanding Basic High-Speed Layout
Speaker: Keven Coates, Geospace Technologies

What is a wire? At high speeds, it behaves very differently from what we were taught in college. This presentation on high-speed basics helps make the subject intuitive in a way that’s rarely presented. Learn about how frequency enters the picture, high-speed signal propagation, impedance, noise, and reflections, with easy-to-understand animations and analogies to understand this subject on a deeper level.

Who should attend: PCB Designers, System Designers, Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner

1:00 p.m. – 4:30 p.m.
33: HDI Routing Solutions
Speakers: Susy Webb, Fairfield Industries

With the pitch of the parts getting tighter and the pin count going up, there is a need to get as much routing, on as few layers as possible, into very dense areas of the board. Those who have not ventured into using HDI yet will find the technology requires different setup and thought about what is important and how to accomplish it. Questions include what via structure to use, what via fan-out pattern is needed, if via-in-pad would be useful, and will the area require routing channels? Additionally, one must think about the layer structure that will be used for return and impedance control, the trace width and spacing needed, how a signal can travel from this layer to that layer, and if the stackup will require more than one lamination. We will discuss the benefits of microvias to electronics, as well as their types and cost compared to through-hole boards, including many pictures and examples of how to work with them.

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Intermediate

 
34: Designing the Interface for DDR 3/4 and PCIe 3/4 Buses
Speaker: Robert Hanson, Americon

This session will start by defining the technology generation, clock rates, memory sizes, voltages, terminations and packaging (BGAs for DDR 3 and4). DDR internal timing will be discussed: column addr strobe, row addr strobe, CAS to RAS delay, RAS pre-charge delay, latency and command rate. Next, the external bus will described with a detailed discussion of the following DDR BUS features: DIMM fly-by topology, on-chip termination (OCT), DQ and DQS, clock structure, CMD and address structure, address and CMD daisy-chain routing, and matching transmission lines. Differences between UDIMM, RDIMM and SDRAM will be specified, along with design changes between DDR 2/DDR 3 and 4. A detailed set of layout guides for PCB design engineers for both UDIMMs and RDIMMs will be provided, along with command and address guides for SDRAMs. Next, the PCIe differential bus will be explained: clock rates, data rates, PLLs, encoding schemes and data transmission overhead. Differential pair layout guides for microstrip, edge couple and broadside coupled stripline configurations, providing the proper trace width, conductor spacing and pwr/gnd layer spacing for ideal high-speed data transfer capability. Finally, thoughts will be provided on the PCIe 4.0 specs (8GHz clock and 16GHz data rate) and whether it is possible to design at this frequency.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Advanced
 
35: RF and Mixed Signal Board Design
Speaker: Rick Hartley

This session is intended to give board designers an understanding of the “things” RF engineers request during PCB layout. Due to sensitivity in analog circuits, the keys to full functionality (whether designing very high-frequency analog PCBs, mixing RF with digital or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the PCB.

This course will cover impedance matching and balance, signal wavelength, propagation delay, critical trace length, noise, reflections, waveguides and other RF transmission lines, ¼ wavelength couplers and filters designed into board copper, layout techniques and strategies, plane structures, component placement, critical routing and circuit isolation, ground plane splitting (when to and when not to), mismatched loads and other discontinuities, signal splitters, tuning transmission lines, power bus decoupling for RF vs. digital circuits and PCB stackups for mixed RF and digital circuits. (Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared for board designers.)

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
36: The Basics of PCB Fabrication
Speaker: Paul Cooke, FTG Circuits

Today's printed boards are quite complex, demanding many new or enhanced fabrication processes. This course will provide a detailed description of the fabrication process, with a special look at how specific design decisions affect the manufacturability of the printed board. Actual panels taken from each fabrication process will be reviewed and discussed. The seminar concludes with a pictorial slide review.

Attendees will learn the PCB manufacturing process steps; material selection; small hole technology; imaging, etching and plating; how design decisions affect PCB manufacturing; and cost drivers.

Who should attend: PCB Designers, Fabricator Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
3:00 p.m. – 4:00 p.m.
37: Demystifying Simulation – Adopting the Right Mentality, and Identifying the Appropriate Tool to Validate your High-Speed Signals
Speaker: Nitin Bhagwath, Mentor Graphics

Designing a board involving high-speed traces can be a daunting task. One common strategy to help increase the likelihood of the board working correctly the first time is to simulate the board before releasing it for fabrication. However, as speeds and complexity have increased, so have the types of tools available for such simulation validation. There are 2D, 2.5D and 3D wave-solver simulators. In addition to traditional wave solvers, other tools help validate the integrity of a high-speed layout. Given this plethora of tools, it is often daunting to determine which tool is applicable under which circumstances. What are the differences among the tools, and more to the point, in what situation should each be used? If you use the wrong tool in a given situation, you could either excessively delay the project, or possibly receive a board that doesn't work correctly at the desired speeds. If you're interested in understanding how industry standard simulation can be used to improve your design process, you'll likely be interested in this presentation.

Who should attend: Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner
Wednesday, September 13th - Free Sessions
9:00 a.m. – 10:00 a.m.
F1: Electromagnetic Fields and Signal Integrity
Speaker: Doug Brooks

Signal integrity issues and electromagnetic fields are tightly intertwined. Much can be inferred about SI issues by visualizing the electromagnetic field around a trace or a pair of traces. In fact, are you aware that the characteristic impedance of a trace is determined more by the electromagnetic field than by the trace dimensions? Or that the propagation speed of a signal is determined by how fast the electromagnetic field can travel? Come hear how, if you learn to visualize what the electromagnetic field looks like, you can make significant judgments about related signal integrity effects.

Who should attend: PCB Designers, SI Engineers, Circuit/Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
F2: Why the Best PCB Designers Use Power-Aware Rule Checks
Speaker: Dr. Zhen Mu, Cadence

As board design complexity increases and power supply-induced noise contributes more and more to the signal noise budget, PCB designers today are facing new challenges to efficiently produce complex designs with high-speed serial links and memory buses. Design rules, or constraints, are heavily used in what some believe is a “signoff” flow to initiate (pre-layout stage) and verify (post-route stage) a PCB design. The potential problem in such commonly used “signoff” flows is they do not have rules to check power-signal interactions. Because the same assumptions that refer to ideal power/ground planes in the pre-layout stage are also used as constraints in the post-route stage, information is missing from the supposed “signoff” flow. As a result, any power-induced noise on signals is not detected. For example, signal via noise traveling through a ground or power plane adds extra crosstalk to non-neighboring signal nets and causes unexpected coupling effects that could exceed a crosstalk budget. This flaw in the supposed “signoff” flow can fool designers into releasing a PCB design with undetected errors. This paper reviews commonly used design flows and introduces why the supposed “signoff” flow based on purely physical rule checking is incomplete. PCB designers should ask questions such as can the design flow I’m using today check for problems caused by power-signal interactions? Is there a power-aware checking method included in my sign-off process? The paper presents a complete power-aware checking scheme that will allow PCB designers to answer, “Yes” and modify their flow to become a true design “signoff” flow.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
10:00 a.m. – 11:00 a.m.
F3: Routing Complex Interfaces Utilizing Intelligent Design Planning Techniques
Speaker: Michael Catrambone, Cadence

Intelligent planning plays a critical role through all stages of the design process. Looking at interfaces from a hierarchical level while fine-tuning and optimizing connections lowers your risk of unexpected rip-ups at the wrong time late in a project. This paper will talk about the design challenges encountered by PCB designers today and how careful planning of these complex routing interfaces can accelerate routing and tuning signals by as much as 75%. The paper also provides techniques designers can apply to break out sequencing, point-to-point routing, and signal tuning.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
 
F4: Choosing the Optimum Substrate Material on ATE PCBs for Digital Video Product with 3GHz and Above Frequencies Using Simulation
Speaker: Eric Cuaton, Analog Devices

High-speed applications in PCBs specifically for automated test equipment are no longer a special case but have become almost the norm. Digital video products (DVP) need test boards that could maintain commendable signal integrity on high-frequency signal test requirements such as high-definition multimedia interface (HDMI) and double data rate 2 (DDR2). When handling ATE boards with high-speed characteristics (i.e., >300MHZ), most PCB designers resort to designing the PCB with a special substrate with low dielectric constant material. 

Who should attend: PCB Designers, Hardware Engineers, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
11:00 a.m. – 12:00 noon
F5: Overview of Multifaceted Impedance Issues
Speaker: John Coonrod, Rogers Corp.

Impedance is an electrical property of circuitry impacting many different aspects of PCB technology. Having a good understanding of impedance behavior can be critical for circuit testing, circuit design and the electrical performance of numerous applications. This presentation is a practical overview of many different concepts of impedance. However, basic theory will be covered for the various topics addressed. To start, impedance definition and performance will be discussed for several common structures found in the PCB industry: microstrip, grounded coplanar waveguide and stripline. Following will be many practical aspects of impedance behavior, such as impedance matching, reflections and PCB fabrication effects. Additionally, testing issues will be addressed such as the rise in impedance over length, sharp corner effects, stepped impedance structures and masking effects.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers, Fabricator Engineers/Operators, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner
 
F6: PCB Cost Drivers
Speaker: Behrooz Shamsodini, NCAB Group USA

This session will help designers, NPI teams, project managers and purchasing professionals better understand the features in a PCB design that influence cost and production manufacturing performance. The module will cover base material selection, board feature design considerations, final finish options and DfM issues that drive cost. The objective is to give basic guidelines that will facilitate design decisions based on design constraints that influence manufacturability and other factors that drive costs. Topics to be covered: material and final finish selection (types of materials, final finish types, relative material/final finish costs, design for production, on-/offshore material sets); hard cost drivers/design influenced (panel utilization, line/space/feature proximity, hole size/quantity/proximity to features, board thickness/layer count/copper weight, final copper thickness/holes and surface, hole fill/materials/cap plating, routing/v-score/profiling, impedance control, high-speed considerations, HDI construction methods and relative costs); soft cost drivers; recommendations.

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Intermediate
1:00 p.m. – 2:00 p.m.
F7: 10 Common Errors in PCB Designs, and How to Catch Them
Speaker: Dave Hoover and Ray Fugitt

We’ve talked to many of the largest PCB manufacturers in the US and abroad. We have developed a list of the most common errors they found on incoming designs. We started with 10; now, based on popular demand, we’ve expanded that list! We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. Methods we will look at include netlist comparison, design for manufacturing, and design rule analysis. After this seminar, the PCB designer will be able to use existing tools in the market to produce better and more accurate designs.

Who should attend: PCB Designers, Fabricator Engineers/Operator
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
F8: Electrical-Thermal Co-simulation for Die-Package-Board
Speakers: Jay Shah, Cadence

Power supply is the heart of any system. As system complexity and operating speeds increase, the power consumption of integrated circuits increases dramatically. Higher-density, high-pin-count components have large via fields, and their associated anti-pads create a “Swiss cheese” effect in the power distribution layers of IC packages and PCBs. Every ASIC requires stable, robust and constant voltage supply for apt operation. With advanced nodes technology like 16nm, 14nm, and 7nm, supply voltage levels are shrinking to 1.2V and below. So when the operating voltages are reduced, noise margin reduces exponentially. It is essential to detect DC problems in the early phase of design to ensure “there is no excessive IR drop, no high-voltage level at devices, high current density or power loss, or high temperature on any physical objects.” The IPC standard provides a manual procedure to estimate localized temperature, but using such a crude method can lead to unsafe or costly designs. High temperature due to localized current density can cause a smoke or fire hazard on a PCB. On one side, running just electrical simulation (IR drop) will result in underestimated IR drop because, when the trace carries current, there is a rise in temperature that lowers the conductivity and eventually increases IR drop. On other side, running IR drop with uniform temperature and conductivity results into overestimated IR drop. Hence, electrical-thermal co-simulation should be the approach for any effective and accurate IR drop analysis. This paper shows how PowerDC electrical-thermal co-simulation assist in computing accurate IR drops, current density, thermal issues with die, packages and PCBs. It considers the coupling between electrical resistance and temperature and estimates temperature at every via/ball/pin on a PCB. PowerDC possesses an adaptive finite element meshing and multi-grid method using which solver recognizes independently sensitive areas. This renders the simulation faster. This analysis will in turn help determine power/ground plane metal shape orientation, thickness, placement of sources and sinks, and locations of power and ground vias.

Who should attend: PCB Designers, Hardware Engineers, SI/PI Engineers

Course rating: Beginner

2:00 p.m. – 3:00 p.m.
F9: Via Currents, Voltages, and Temperatures: The Story That Grew and Grew!
Speaker: Doug Brooks

Douglas Brooks has just completed a two-year research collaboration with Dr. Johannes Adam, Leimen, Germany. The collaboration started out as an effort to measure the thermal gradient on a trace. It extended to determining the temperature of a via. And by the time they were through, the research involved the contributions of 7 other people and/or organizations and a book. Come hear about why what we thought we understood about via temperatures is totally incorrect, and how this story just grew and grew from there.

Who should attend: PCB Designers, SI Engineers, Circuit/Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
F10: IPC-2581 Digital Data Transfer Success Stories and Future Direction
Speaker: Hemant Shah, Cadence

Leading systems companies, PCB manufacturing companies and software providers are successfully using the IPC-2581 open, global standard to streamline design data handoff for fabrication, assembly and test. Although the 92 consortium members report success with thousands of designs, this neutrally-maintained, vibrant standard is expanding its value proposition to address new technologies. The IPC-2581 Consortium expects industry-wide adoption over the next few years. The multi-company panel will provide updates on IPC-2581 adoption success stories, consortium activities to support, validate and adopt the latest versions, what data augmentation beyond ECAD is and why it is important, and the future direction for the standard.

Who should attend: PCB Designers, Fabricator Engineers/Operators, Assembly Engineers/Operators, Test Engineers, Other
Course rating (Beginner, Intermediate, Advanced): Beginner
3:00 p.m. – 4:00 p.m.
F11: Shortening the Chain
Speaker: Greg Papandrew

How does one best work directly with a PCB manufacturer? Is it okay to work with more than one? This session will review expectations of a good vendor, conducting an audit, the daily maintenance, quality issue resolution, and customer support/communication.

Who should attend: PCB Designers, Fabricator Engineers/Operators, Assembly Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Level: Beginner, Intermediate
 
F12: EDA Support and Roadmap for 3D Printing of PCBs
Speaker: Humair Mandavia, Zuken

The rapid evolution and widespread use of 3D printing technology brings with it new approaches to the market for electronics design and manufacturing. At the same time, the increase of new applications with molded interconnect devices (MID) and inkjet printing has spurred the growth and adoption of additive manufacturing. This presentation will cover the convergence of these technologies for 3D printing of printed circuit boards, along with some of the key challenges and opportunities in this space. Printing of electronics is unique from other applications, so we will explore how to leverage new technology to support it, along with some of the other capabilities and content that will be required as part of the EDA roadmap.

Who should attend: PCB Designers, System Designers, Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
4:00 p.m. – 5:00 p.m.
F13: Achieving Seamless Electro-Mechanical Collaboration
Speaker: David Wiens, Mentor Graphics

In most PCB system designs, tight synchronization between the electrical and mechanical flows is required to ensure both disciplines are correctly aligned for fabrication, ultimately decreasing design effort and optimizing for form factor. Given the dynamic parallel nature of design (and additional issues with a geographically distributed team), the potential for miscommunications (and resulting redesign) has risen dramatically. This session will evaluate the merits of different design flows and collaboration approaches, and identify some best-practice opportunities to streamline your design process (without having to become a mechanical design tool specialist).

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Beginner
 
F14: How Involved Should Designers be in Stackup Decisions?
Speaker: Walter Ofer Abramsohn, Frontline

With the automotive industry driving radar technology at 77GHz, and new wireless networks requiring 60GHz, PCB production is becoming ever more challenging. Before board production can begin, every detail must be planned, from material selection and impedance matching to dielectric thicknesses and metal roughness. Should designers include these decisions in the design process, or should they rely on the fabs? How best should designers collaborate with the fab on high-end stackups? In this session, you’ll explore current PCB challenges and how they affect today's stackups; discover ways to build a fully enclosed design environment that includes a realistic model of your board and enables a closed-loop simulation; learn how to best collaborate with the fab by distinguishing between tasks that are part of the board design process and tasks to be left to the fab’s discretion, and learn how to include the fabricator’s final stackup data in the simulation environment.

Who should attend: PCB Designers, Hardware Engineers, SI Engineers, Fabricator Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
Wednesday, September 13th - Free DFM/DFA/DFX Sessions
9:00 a.m. – 10:00 a.m.
F15: Design, Fabrication, Assembly of IoT PCBs
Speaker: Zulki Khan, Nexlogic

The PCB of an IoT device is a different beast from the traditional one, which is substantially larger and mostly rigid. IoT devices, on the other hand, consist mostly of either rigid-flex or flex circuit assemblies, which come with their own set of design layout, fabrication, and assembly considerations. This presentation takes the IoT OEM through various stages of design layout, fabrication, and assembly, and the important considerations that must be accounted for to bring an IoT device to a successful beginning. Top considerations at design layout include signal trace thickness, number of rigid and flex circuit layers, copper weight on these layers, through-hole placement, CTE, and stiffener placement. Top considerations for fabricators include strong adhesions between layers on rigid and flex circuit sides, knowing the critical calculations, understanding when current transfers from rigid to flex side, understanding nuances of small components like 0201s and 01005s, PoP, fine-pitch BGAs, tight tolerances in terms of BGA footprints, laser direct imaging for solder mask on the board, and laser drill for via drilling. Ensure vias are completely planar. If they’re not, via-in-pads leave bumps, creating imperfect joints and intermittent connections. Top considerations for assembly include special fixtures and tooling for proper placement, special fixtures for planar rigid-flex boards, and cure epoxy using UV light.

Who should attend: PCB Designers, System Designers, Fabricator Engineers/Operators, Assembly Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Intermediate
10:00 a.m. – 11:00 a.m.
F16: How Qualcomm Reduced Package Design Validation by 80%
Speaker: Jay Gorajia, Mentor Graphics

Ubiquity of mobile devices such as smartphones and tablet PCs, a heightened need for computing power, and an accelerated growth of Internet of Things (IoT) are sweeping the globe. Market demand for more functionality in an ever-shrinking space is driving the need to increase functionality of ICs, further adding to already complex packaging to accommodate high-pin-count designs. IC packaging is now a critical link in the silicon-package-board design flow. Electronics design companies like Qualcomm continuously strive to accelerate new product introductions (NPI) at the lowest total cost, while still attaining the highest level of quality, in most cases outsourcing manufacturing. Qualcomm is one of the best-in-class organizations, which are 68% more likely than their peers to use design for manufacturing (DfM) validation to help eliminate manufacturing defects, reduce revision spins and improve design-to-market time. Qualcomm, as leader in package design technology, decided to improve the validation process to remain competitive by focusing more time on value-added design actions. Qualcomm’s package design group is responsible for assessing conformity and quality of the package design based on agreed constraints between Qualcomm and its manufacturing partners, all of which are defined in an Excel file. Designers would then manually review each package design against these rules. This was a tedious and time-consuming task. This presentation will describe how Qualcomm integrated IC package design validation automation into the package design flow. As a result, Qualcomm’s designers are able to validate their designs against their manufacturer’s rules seamlessly, and reduce the risk of revision spins and delays in time-to-market.

Who should attend: PCB Designers
Course rating (Beginner, Intermediate, Advanced): Intermediate
11:00 a.m. – 12:00 noon
F17: Variables Affecting Bare PCB Warpage during Reflow: A Study on Support Methods and Temperature Uniformity
Speaker: Neil Hubble, Akrometrix

Many of today’s PCB designers may consider the effects of temperature change on the PCB during the design process. Details such as copper balancing can be critical to reduce warpage seen during a reflow cycle. However, the magnitude of PCB warpage can vary widely independent of the PCB design, and dependent on the conditions under which the board experiences the reflow cycle. Current industry standards exist covering general flatness requirements for PCBs, along with recommendations for measuring local warpage over temperature where surface mount components are attached. To better control warpage over temperature, critical variables to PCB warpage must be better understood. This paper shows a case study of multiple bare PCBs. Attempts are made to control moisture exposure, heating and cooling rates, reflow cycle quantity, and the warpage metrology technique. The study uses the shadow moiré technique to measure PCBs as they are heated through realistic reflow profile timing and temperatures. Warpage measurements will be made at critical points in time and temperature during the profile. The study will focus on two variables across multiple PCB types: 1) Temperature uniformity of the PCB. As most PCBs are heated through a reflow oven on a belt conveyor, they have a leading edge with a higher temperature. 2) Sample support method of the PCB. Gravity plays a role in warpage over temperature. Thus common PCB support methods are used for warpage comparison over temperature

Who should attend: PCB Designers, Hardware Engineers, Fabricator Engineers/Operators, Assembly Engineers/Operators, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
1:00 p.m. – 2:00 p.m.
F18: Embedded RFID - Traceability for PCBs
Speaker: Gernot Seeger, Beta Layout

RFID is a prerequisite for IoT and begins at the PCB production level. Whether for production process control, product security or recycling, the electronics industry requires a new identification solution. The roadmaps for the Internet of Things and Industry 4.0 are based on smart products that should guarantee close traceability: products tagged with RFID modules. By embedding an RFID module into the board, every PCB is identifiable from the cradle to the grave. RFID simplifies identification by eliminating the need for barcodes and line of sight, creating a systematic and more efficient solution. Each RFID module carries a worldwide unique identification number and additional user memory. The user memory can be used to store information useful in the product’s lifecycle to the final recycling step. The latest method to make electronics smart will be introduced. PCBs with embedded RFID enable wireless communication without line of sight and make electronic products traceable, identifiable and safe, not only during the production process but for the entire product lifecycle. Therefore, embedded RFID is not only a substitute for known identification systems but enables the use of only one technique for the whole value-added chain.

Who should attend: PCB Designers, Fabricator Engineers/Operators, Assembly Engineers/Operators, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
2:00 p.m. – 3:00 p.m.
F19: System Design – Designing and Collaborating Across Multiple Disciplines
Speaker: Craig Armenti, Mentor Graphics

Designs containing multiple interconnected boards are traditionally developed with desktop office tools such as spreadsheets for intra-board connectivity, text files for system element parameters, and drawing applications to show block-level system structure and hierarchy. These disconnected tools and processes limit collaboration between the multiple disciplines that comprise the typical product development team, resulting in costly intra-system connectivity errors, extensive, time-consuming manual validation steps, and restrictive system change rules that prohibit system design optimization. Proper collaboration is key to achieving accelerated design targets with large, sometimes globally distributed teams. Leveraging the power of the team requires utilization of design flows that enable maximum productivity. During this session we will discuss how to improve design team productivity and reduce development cost by moving away from inefficient paper and manual processes toward an automated, fully integrated, collaborative workflow. An integrated flow enables synchronization among all levels of abstraction, along with automated connector management, helping design teams collaborate across disciplines and realize their time-to-market targets.

Who should attend: PCB Designers, System Designers, Hardware Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner
3:00 p.m. – 4:00 p.m.
F20: 3D-MID Design and Manufacturing
Speaker: Gernot Seeger, Beta Layout

Since electronic devices become smaller and more precise, engineers face the challenge of developing modules that need less space and are lower in weight. The new 3D-MID (mechatronic integrated devices) technology, plastic parts designed with electronic circuits, is a favorable solution and the answer to the requirements of the electronics industry for space-saving modules. Three-dimensional circuit carriers enable engineers to develop multifunctional products with new features and reduced weight. 3D-MIDs are usually produced from injection molded plastic. A new method by using 3D prints instead of molds allows more economic production of MID-prototypes in less time. This presentation covers how 3D-MID prototypes based on laser-sintered 3D prints are manufactured and shows how this technology will be accessible for a broad range of R&D engineers. The presentation will answer questions regarding necessary data, design rules and manufacturing. Conclusion: 3D-MID prototyping will be less expensive and quicker by using 3D printed parts instead of injection-molded parts. By providing an appropriate 3D MID design software and offering a complete prototyping service, this technology also can be used by smaller companies and (independent) R&D engineers.

Who should attend: PCB Designers, Hardware Engineers, Fabricator Engineers/Operators
Course rating (Beginner, Intermediate, Advanced): Beginner
4:00 p.m. – 5:00 p.m.
F21: It’s Never Too Early to Avoid DfX Issues
Speaker: Edward Acheson, Cadence

Preventing design defects that reduce manufacturing yield is everyone’s business. An ideal way to improve your design schedule is to eliminate change requests from your PCB fabricator by identifying issues and fixing your design before handoff. This paper will show an approach of detecting DfX issues early and how this can eliminate unnecessary iterations for fixing issues. It will show how PCB designers can easily check for insufficient spacing between objects, wrong pad/ring sizes, threats of acid traps, missing mask elements, etc. Making sense of the results with cross-probing back to the PCB design expedites the process of finding and correcting errors at the source. Come share your experiences with the group with what steps your team took to improve your designs’ manufacturability before handoff.

Who should attend: PCB Designers, Fabricator Engineers, Operators, Assembly Engineers, Operators, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
Wednesday, September 13th - PCB Fabrication/EMS Management Forum
9:00 a.m. – 10:00 a.m.
M1: How 3D Printing Hardware and New Materials are Changing the Face of Manufacturing
Speaker: Matthew Fielder

Manufacturers and engineers are increasingly interested in a_ordable, large format, industrial 3D printing. re:3D will share insight and experience with the challenges and bene_ts of large-scale additive manufacturing. Several key barriers prevent wider adoption of 3D printing in the industrial space. We will discuss applications driving the technology forward and how, utilizing improved materials, hardware, and process knowledge, your engineers and designers will be better poised to maintain a competitive edge.

10:00 a.m. – 11:00 a.m.
M2: 3D Printing: A New Dimension in Electronics Prototyping & Manufacturing
Speaker: Simon Fried, Nano Dimension

This presentation will cover the various aspects of 3D printed electronics, from material science to formulation, physics and overall printing process, including curing and sintering of high-performance nano-conductive and dielectric inks. It will highlight the many advantages of 3D printed electronics for rapid development and manufacturing, including in-house rapid prototyping of multilayer circuit board prototypes, reducing time to build from weeks to just hours, saving time and money and protecting intellectual property. Moreover, additive manufacturing of electronics can improve efficiency and make complexity free. The presentation will discuss the potential for using additive manufacturing for electronics, including applications. It will discuss the many challenges of developing a professional 3D printer for electronics and introduce Nano Dimension's unique products, including the first 3D printer dedicated to printing multilayer PCBs and 3D circuitry, including real-life applications. 3D printed electronics will allow designers to produce circuitry within objects, rather than designing circuits to be inserted into a device.

11:00 a.m. – 12:00 noon
M3: How to Set Up a Successful Blind Via Hole Fill Plating Process
Speaker: George Milad

Blind vias that connect layer 1 to layer 2 or to layer 3 are an enabling technology for HDI (high density Interconnect) type boards. Via fill makes for a robust connection with no chance of any voids during assembly. Vias with 1:1 aspect ratio are common, and it is possible to plate vias that are deeper than the diameter of the via up to 1.2:1. Successful via _ll plating requires a specific electrolyte; the copper concentration is as high 50 – 60 g/L copper with low sulfuric acid at 30 – 60 g/L. This is combined with a unique organic additive combination with a prominent leveling component. The leveling component acts predominantly on the surface and suppresses the surface plating allowing the brightener and carrier combination to plate up from the bottom of the via, for filling to occur. Ideally the solution movement must be vigorous and parallel to the surface (laminar_ow); this ensures adequate leveler replenishment.

The mechanism of via filling is very different from thru hole plating. A good understanding of the following variables is paramount to the success of the process:

  • The electrolyte
  • Pre-dip or no Pre-dip
  • The additives, CVS
  • Aspect ratio of the via
  • The plating cell setup
  • Recti_cation and plating cycles
  • Panel vs Pattern Plating
  • Voids in the plating
  • Voids in the plating
  • Post-plate planarization

The optimization of each of these variables will be the topic of this presentation.

1:00 p.m. – 2:00 p.m.
M4: Five-an-a-Half Technical Services Marketing Myths
Speaker: Susan Mucha, Powell-Mucha Consulting Inc.

Getting results in technical services marketing activities is a lot like designing a product. A creative effort with no focus on differentiation, design rules, DfX or end-market hot buttons will not be money well spent. This presentation looks at common marketing myths and the “design” rules and best practices that lead to a sustainable sales funnel.

2:00 p.m. - 3:00 p.m.
M5: Putting Lipstick on a Minnow: The challenges and pitfalls of making a small Silicon Valley tech business interesting to interns
Speaker: Robert Boguski, Datest

Internship programs are one important means by which tech companies maintain a pipeline of potential new talent from among university graduates. This is a special challenge for small companies that must compete for the attention of new talent against the glamor and amenities offered by well-known Silicon Valley name brands. The speaker will share his personal experiences regarding what works and what doesn’t when pitching a small but earnest test engineering firm as an attractive place to work and learn for summer engineering interns. Along the way, he may have something to say about the continued dearth of female engineering talent in oh-so-liberal Silicon Valley, as well as the practicality of working with so-called second- and third-tier universities and colleges, rather than the obvious (arrogant) suspects, as reliable sources of that talent.

3:00 p.m. - 4:00 p.m.
M6: Suspect Counterfeit ESD Materials and Packaging Protection for EEE Parts Can Lead to Incoming Inspection, Materials Handling and Longterm Storage Issues.
Speaker: Bob Vermillion, RMV Technology Group

 First to present and publish on suspect counterfeit ESD materials and packaging in the DoD supply chain for the NASA Quality Leadership Forum in 2010, Bob Vermillion will present an interactive white paper on the impact of suspect and nonconforming packaging issues impacting global logistics and materials management. Taking a fresh look at the escalation of suspect counterfeits in the procurement process for product selection, this talk will discuss the value of periodic verification of materials and packaging beyond first article, and the consequences of not having a program in place, including examples and long-term storage issues.  As a first step, implementation of an incoming materials inspection program should be considered. The first line of defense is to test the package.  

5:00 p.m. – 6:00 p.m. Evening Reception, sponsored by EMA Design Automation

Thursday Sept 14th

Thursday, September 14th
8:30 a.m.
Conference Coffee Break, sponsored by Prototron Circuits
8:30 a.m. – 12:00 noon
38: BEYOND Simulation – There’s So Much More You Can Do!
Speaker: Susy Webb, Fairfield Industries

Simulation is a great tool, but it’s not the only tool for predicting a high-quality board that has low noise, good signal integrity, manufacturability, and performs well while in service. In this presentation, we will show how the designer’s knowledge of basic electronics and physics can be used to understand how the signals will actually flow and return within the board structure. We will discuss how to control that high-frequency energy with spacing, planes, stackup, and layer paired routing. Even if signals are not designated as impedance-controlled signals, controlling their impedance throughout helps control reflections, crosstalk, false triggering, and EMI (noise). Parts can be placed and routing can be done in a manner that will also help control EMI. The power and ground distribution can be carefully planned with capacitor and plane placement so the design will be able to handle the power needs of the parts while in operation. Other topics covered include some manufacturability issues, so the designer can use this knowledge to help get the best possible results

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Intermediate
9:00 a.m. – 11:00 a.m.
39: The Mystery of Bypass Capacitors
Speaker: Keven Coates, Geospace Technologies

How do you design a high-speed digital circuit with enough bypass caps in the right area to supply all the peak power demands? You can’t listen to all the expert advice because it seems they can’t even agree! This presentation covers power distribution network basics and shows three approaches with simulation results for each, and some real-world experience and advice on bypassing for high-speed circuits. 

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
 
40: Mechanical Issues Affecting EMI
Speaker: Rick Hartley

As most engineers and designers are aware, EMI occurs because some mechanical structure, within or attached to our system, is capable of resonating and radiating electro-magnetic field energy. Those mechanical structures can be a cable attached to the housing around our circuit boards, a part of the metal chassis, a slot in the chassis or a portion of one of the circuit boards in the system. Knowing how to control these structures so they aren’t capable of supporting resonance and radiation is the key to success.

This course will discuss basic physics of energy movement, metal vs plastic enclosures, slots and openings in enclosures, shielding enclosures, shielding of components, proper shielding of cables, basic component placement for MEs, extreme importance of I/O connector placement, routing of external cables, position of cables inside the system, multiple boards in the system – best arrangement, heatsinks – potential EMI problems, using chassis as a heatsink, and other items MEs need to know about PCBs.

Who should attend: PCB Designers, Mechanical Designers/Engineers, Circuit/Hardware Engineers, System Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
 
41: Power Integrity Improvement in FPGA Boards Using Embedded 1-Port Vector Network Analyzer
Speaker: Dr. Cosmin Iorga, NoiseCoupling.com

This workshop starts with a short presentation of power integrity fundamentals and continues with hands-on experimental analysis and optimization of power integrity on a PCB board with an FPGA. Free kits containing an FPGA PCB board, a set of decoupling capacitors, a USB cable, and software on a CD-ROM will be provided. Participants will program the FPGA to function as a 1-port vector network analyzer (VNA) and install the software on their computers (Windows-based notebook computers). Next, they will connect the FPGA board to the computer using the USB cable. Using the software on the computer, participants will then control the 1-port VNA to measure the impedance profile of the power delivery network from 1Hz to 600MHz. This is the impedance of the power delivery network as seen by the FPGA on-die logic circuits, including the power supply rails on the die, package, and PCB, all the way to the voltage regulator. The impedance profile (1Hz to 600MHz) will be displayed. We will discuss the resonance peaks on the impedance graph and the mechanisms that generate them. Next, participants will use the software to extract a 1-port S-parameter model of the power delivery network (PDN) using the VNA loaded in the FPGA. Then we will use this S-parameter model to simulate the supply noise on the FPGA power rails. In the simulation, we will use an example FPGA project for which we will create the transient supply current profile in a .vcd file format. Next we will use a Spice circuit simulation tool to create a test bench containing the FPGA transient current source and the 1-port s-parameter model extracted from the FPGA board. We will run a transient simulation and evaluate the supply noise results. We will compare the noise with the FPGA specifications and analyze how far the noise exceeds the specifications. We will define a target impedance that represents the maximum allowable power delivery network impedance over the operating frequency range. Then we’ll optimize the decoupling capacitors through an iterative process. We will use the set of capacitors in the kit to replace the decoupling capacitors on the FPGA board and re-scan the PDN frequency profile using the 1-port VNA loaded in the FPGA. For each iteration we will save the measurements and compare resonance peaks among various decoupling capacitor combinations. After a few iterations, the impedance is expected to drop below the target value. At this point we will re-extract an S-parameter model using the 1-port VNA loaded in the FPGA, and we will plug this S-parameter model into the test bench and re-simulate the supply noise to validate it is within the FPGA specifications. We will conclude with an analysis of the power supply noise improvement process from the initial design to the optimized one.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
9:00 a.m. – 5:00 p.m.
42: The Complete Guide to Understanding Transmission Lines
Speaker: Robert Hanson, Americon

This all-day tutorial covers the fundamentals of frequency, time, and distance; lumped versus distributed systems; EM fields; geometry, C, L, and Zo interrelationships, and C&L resonance. Also covered are transmission line characteristics, including the quality factor, Q, and why lumped circuits can ring and cause EMI; infinite uniform transmission lines; effects of source and load impedance; special transmission line cases; determining line impedance and propagation delay using TDR and VNA; skin/proximity effect and dielectric loss; the capacitive load: Zo and propagation delay; matching Zo with trace alterations (neckdowns): minimizing the C load; characteristics of T. lines: coax, pair, microstrip, buried microstrip, stripline and differential: asymmetric, dual, edge; and 90o, 45o bends. Are they concerns?

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
 
43: Design for High Reliability PCB and Assemblies
Speaker: Paul Cooke

Today’s designs cover a plethora of technologies from low to high densities, analog, digital, low-speed and microwave, to name a few. We have rigid circuit boards, flexible circuit boards and rigid/flex circuit boards. We add and/or subtract copper and other metals. All of these technologies share a common goal: cost, performance, and reliability over time. In this session we will explore several not-so-evident factors that affect the reliability of a product.

As part of the general experience, we will split into small discussion groups that will explore, under guidance, the issues that affect reliability for the most common technologies. The groups will look at new and innovative ways to test and verify a product’s integrity in both leaded and lead-free products. There will be ample time allocated to look at individual challenges faced by the attendees. Attendees will gain a clear understanding of overall DfM issues that affect product reliability, how to apply learned principles to their designs, lead-free DfM/DfR considerations, and what notes should be placed on the fabrication drawing.

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Intermediate
11:00 a.m. – 12:00 noon
44: Empowering a PCB Designer to Add PDN Analysis Value to their Organization
Speaker: John Carney, Cadence

PCB design is getting intense, and the market is competitive. How can a PCB designer become more valuable to their organization? One approach is to take a bigger role in the analysis aspect of their layout. PDN analysis is no longer the domain of just the engineering signal integrity experts. This paper presents a new methodology where graphical PowerTree data lets a designer visualize and analyze their complex PCB power delivery network with the goal of achieving power integrity criteria. This solution, coupled with automatically calculated IPC constraints, enables a user to know the proper values for common PDN rules. These features empower a PCB designer to become a part of the PDN solution during the design process.

Who should attend: PCB Designers, Hardware Engineers, SI Engineers, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
12:00 noon – 1:00 p.m.
Polar Instruments Lunch-n-Learn
(Thursday conference attendees and speakers only)
1:00 p.m. – 4:00 p.m.
46: Development Lab Techniques to Predict and Avoid Field Problems
Speaker: Douglas Smith, University of Oxford

Field problems are very expensive to service, so avoiding them is imperative in today's competitive environment. This seminar will cover techniques to find hidden flaws in products. Some of the techniques involve injecting signals to simulate the customer environment (but not standard EMC or ESD tests, which often miss future field problems). Signal integrity, EMC, ESD, and other types of problems are addressed by these procedures. An example includes an accelerated life test that exposes equipment to tens or hundreds of thousands of ESD pulses over hours or days of low to medium intensity ESD events (common in the environment) to predict gradual degradation of a product over time. Another uses a special way to inject radio frequency energy into a product (especially analog products) to predict field or compliance problems. There will be live experiments for attendees to operate in which a flaw is installed in a product for them to find. In one case, a small plastic box that has a common flaw inside has caused countless field problems. The attendees, using techniques from the seminar, will find and locate the flaw within the box without opening the box.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers, Test Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate
1:00 p.m. – 2:00 p.m.
47: Accurate 3D Via Modeling for High-Speed Serial Link SerDes Channels
Speaker: Jay Shah, Cadence

Even small discontinuities on high-speed printed circuit boards should be given great attention. With a rapid increase in frequency and rise time (i.e. smaller), even a small change in transmission line impedance (specifically due to PCB vias) will result in signal reflection (and an increase in insertion loss) and hence signal degradation followed by poor system performance. This paper is a comprehensive study on differential via modeling parameters such as drill, anti-pad, stub length and fan-out at pre-layout phase and post-layout phase for high-speed multi-gigabit serial link channels. Interconnects such as microstrip and stripline can be modeled accurately using 2D field solvers. However, for vias, full-wave 3D field solvers are a must. A “design of experiments” approach is exercised to determine the level of influence of these variables and eventually optimize PCB via parameters. To extract the electrical performance characteristics, Sigrity SystemSI Via wizard and Sigrity PowerSI 3D-FEM toolsets are leveraged. With PowerSI 3D-FEM, return loss, insertion loss, inductance and capacitance values are calculated. Further differential via characteristic impedance is investigated with time-domain reflectometry (TDR) simulation carried out using Sigrity Broadband Spice.

Who should attend: PCB Designers, Hardware Engineers, SI/PI Engineers
Course rating: Beginner
1:00 p.m. – 4:30 p.m.
48: Part Placement Choices and Consequences
Speaker: Susy Webb, Fairfield Industries

There are many ways to place parts on any board, but clearly some ways work better for physics, electrical, and mechanical purposes. If a new board works electrically but won’t interface properly with the rest of its system, it may require costly and time-consuming re-design and re-testing. Designers must understand the board, electrical and system needs, as well as typical placement and routing guidelines and the consequences of not adhering to them. When they understand the reasoning behind these things, and the effects they have on one another, designers will intuitively know how to make good decisions for their own boards, avoiding problems. In this presentation, we will discuss choosing effective parts, approximate order of overall placement, placement to set up routing, board and system consequences, manufacturability, and more.

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Intermediate
 
49: Design of Power Distribution and Decoupling
Speaker: Rick Hartley

The power distribution section of a PCB is the foundation around which all things work in the circuit. If not designed correctly, the entire circuit is at risk from noise, to say nothing of the severely increased possibilities for EMI. Low impedance in the power bus of a digital circuit across the range of harmonic frequencies is critical. To further complicate matters, analog and digital circuits often need a much different approach for power delivery to ICs.

This course will cover the major components of the power bus, the distribution path for ICs, medium- and high-frequency decoupling concerns, the importance of IC pin assignments, placement of decoupling in both low layer count and high layer count boards, real performance of capacitors, including inductance of vias, how much decoupling is enough, how many different values of capacitors to use, the importance and performance of power/ground planes, and the importance of board stack.

Who should attend: PCB Designers, Circuit/Hardware Engineers, SI engineers, System Engineers
Course rating (Beginner, Intermediate, Advanced): Intermediate, Advanced
1:00 p.m. – 3:00 p.m.
50: PCB Design Techniques to Improve ESD Robustness
Speaker: Dan Beeker, Freescale Semiconductor

This presentation will provide simple definitions for ESD/EOS, and describe the important differences in the energy involved and the damage that can result. PCB design techniques for improving system robustness will be presented.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
3:00 p.m. – 5:00 p.m.
51: Electromagnetic Fields for Normal Folks
Speaker: Dan Beeker, Freescale Semiconductor

The material presented will be focused on the physics of electromagnetic energy basic principles, presented in easy-to-understand language with plenty of diagrams. Attendees will discover how understanding the behavior of EM fields can help design PCBs that will be more robust and have better EMC performance. This is not rocket science but an easy-to-understand application of PCB geometry.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate

2017 Sponsors

FacebookFacebook
TwitterTwitter
LinkedInLinkedIn

ISSN 1555-7936, Copyright © 2017 UP Media Group Inc., PO Box 470, Canton, GA 30169. All rights reserved.
This website contains copyrighted material that cannot be reproduced without permission. UP Media Group Inc. Privacy Policy